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Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individualdoi:10.1109/hldvt.2006.319966 dblp:conf/hldvt/BouleZ06 fatcat:yx4ng3z2izhfpjzv4biki4geuu