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MIPS architecture is one of the first commercially available RISC processor. MIPS stands for 'Microprocessor without Interlocked Pipeline Stages'. In a normal MIPS RISC architecture, for 32-bit multiply operation it can hold the processor for more than 32 clock cycles, which affects the processor performance. In order to avoid this problem, here we have implemented 32-bit MIPS processor with one CISC operation for multiplication which is realized using a Booth multiplier. Processor is tested indoi:10.17577/ijertv4is110636 fatcat:qqsugbrw3fblvdopvpv7oa6p2y