A doubly-latched asynchronous pipeline

R. Kol, R. Ginosar
Proceedings International Conference on Computer Design VLSI in Computers and Processors  
DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance. It is most suitable for converting synchronous circuits into asynchronous ones. DLAP is capable of truly decoupled operation: All pipeline stages can shift data simultaneously, and execution is faster than previous designs when variable delays are encountered. Implementations based on both edge triggered registers and transparent latches are shown. STG and verified controllers are presented and simulated.
more » ... presented and simulated.
doi:10.1109/iccd.1997.628942 dblp:conf/iccd/KolG97 fatcat:ccqh6wr3kjblvjsfdtgsqfizf4