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High-speed architectures for digital image processing
1987
IEEE Transactions on Circuits and Systems
Absiract-This paper introduces the problem of and presents some state-of-the-art approaches for high-speed digital image processing. An architecture based on distributed arithmetic, which eliminates the use of multipliers, is described. A minimum-cycle-time filter architecture, which features a high degree of parallelism and pipelining, is shown to have a throughput rate that is independent of the filter order. Furthermore, a new multiprocessing-element architecture is proposed. This leads to a
doi:10.1109/tcs.1987.1086238
fatcat:cf22sud3ofazdko6imkipeed3a