SystemC/TLM semantics for heterogeneous system-on-chip validation

Florence Maraninchi, Matthieu Moy, Jerome Cornet, Laurent Maillet-Contoz, Claude Helmstetter, Claus Traulsen
2008 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference  
SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure
more » ... hrony and pure asynchrony. We list the available solutions for the semantics of Sys-temC/TLM, and explain how to connect SystemC to existing formal validation tools.
doi:10.1109/newcas.2008.4606376 fatcat:kvokkd2pzjdbnevslrn7t2cp4a