Optimizing wirelength and routability by searching alternative packings in floorplanning

Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
2008 ACM Transactions on Design Automation of Electronic Systems  
Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a
more » ... ler interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.
doi:10.1145/1297666.1297687 fatcat:ikqistrvojcq7kg4i6v4vc3d2u