Automatic synthesis of reactive agents

Insu Song, Guido Governatori, Loachim Diederich
2010 2010 11th International Conference on Control Automation Robotics & Vision  
This paper introduces a new approach to designing smart control chips that enables automatic synthesis of real-time control systems from agent specifications. An agent specification is compiled into a hardware description format, such as RTL-VHDL (Register Transfer Level-VLSI Hardware Description Language) or RTL Verilog, which is synthesized using computerassisted tools to develop ASIC masks or FPGA configurations. A rule-based specification language called Layered Argumentation System (LAS)
more » ... defined and a sound and complete mapping to Verilog is developed. LAS combines fuzzy reasoning and nonmonotonic reasoning. This enables chip designers to capture commonsense knowledge and concepts having varying degrees of confidence collaboratively and incrementally.
doi:10.1109/icarcv.2010.5707867 dblp:conf/icarcv/SongGD10 fatcat:mwxosnfaifdbnb4bgvfivk4gpi