The interaction of software prefetching with ILP processors in shared-memory systems

Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, Sarita V. Adve
1997 SIGARCH Computer Architecture News  
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such a s m ultiple issue, dynamic scheduling, and non-blocking reads. Recent work has shown that memory latency remains a signi cant performance bottleneck for shared-memory multiprocessor systems built of such processors. This paper provides the rst study of the e ectiveness of software-controlled non-binding prefetching in sharedmemory multiprocessors built of state-of-the-art ILP-based
more » ... s. We nd that software prefetching results in signi cant reductions in execution time (12% to 31%) for three out of ve applications on an ILP system. However, compared to previous-generation systems, software prefetching is signi cantly less e ective in reducing the memory stall component of execution time on an ILP system. Consequently, e v en after adding software prefetching, memory stall time accounts for over 30% of the total execution time in four out of ve applications on our ILP system. This paper also investigates the interaction of software prefetching with memory consistency models on ILP-based multiprocessors. In particular, we seek to determine whether software prefetching can equalize the performance of sequential consistency (SC) and release consistency (RC). We n d that even with software prefetching, for three out of ve a pplications, RC provides a signi cant reduction in execution time (15% to 40%) compared to SC.
doi:10.1145/384286.264158 fatcat:wvaxpdgn6vgxbilvi66lyk7kwu