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Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
2010
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
This paper proposes FlexCore, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. FlexCore provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into a modern microprocessor, the FlexCore architecture allows parallel monitoring and bookkeeping
doi:10.1109/micro.2010.17
dblp:conf/micro/DengLMSS10
fatcat:htxhhfdrmvfm3lwbqtlditg22i