Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
This paper proposes FlexCore, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. FlexCore provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into a modern microprocessor, the FlexCore architecture allows parallel monitoring and bookkeeping
more » ... s to be dynamically added to the processing core and adapt to application needs even after the chip has been fabricated. At the same time, FlexCore is far more efficient than software implementations because its fine-grained reconfigurable architecture closely matches bitlevel operations of typical monitoring schemes and allows monitoring schemes to operate in parallel to the monitored core. In fact, our experimental results show that monitoring on FlexCore can almost match the performance of full ASIC implementations. To evaluate the FlexCore architecture, we implemented an RTL prototype along with several extensions including uninitialized memory read checking, dynamic information flow tracking, array bound checking, and soft error checking. The prototypes demonstrate that the architecture can support a range of monitoring extensions with different characteristics in an efficient manner. FlexCore takes moderate silicon area and results in far better performance and energy efficiency than software.
doi:10.1109/micro.2010.17 dblp:conf/micro/DengLMSS10 fatcat:htxhhfdrmvfm3lwbqtlditg22i