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The design of an asynchronous MIPS R3000 microprocessor
Proceedings Seventeenth Conference on Advanced Research in VLSI
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The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6 m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.
doi:10.1109/arvlsi.1997.634853
dblp:conf/arvlsi/MartinLMNPSC97
fatcat:vz5okylqiva2nejemvgh3bs7xy