Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

David Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David Bull
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 m
more » ... ogy which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments. Index Terms-Adaptive circuits, dynamic voltage and frequency scaling (DVFS), process variations, self-tuning processor, single event upsets.
doi:10.1109/isscc.2008.4523226 dblp:conf/isscc/BlaauwKLMPTDB08 fatcat:g7wmfbxidrgvnfafwgdmx7gyhu