Data-aware process networks

Christophe Alias, Alexandru Plesco
2021 Proceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction  
With the emergence of reconfigurable FPGA circuits as a credible alternative to GPUs for HPC acceleration, new compilation paradigms are required to map high-level algorithmic descriptions to a circuit configuration (High-Level Synthesis, HLS). In particular, novel parallelization algorithms and intermediate representations are required. In this paper, we present the data-aware process networks (DPN), a dataflow intermediate representation suitable for HLS in the context of high-performance
more » ... uting. DPN combines the benefits of a low-level dataflow representation -close to the final circuit -and affine iteration space tiling to explore the parallelization trade-offs (local memory size, communication volume, parallelization degree). We outline our compilation algorithms to map a C program to a DPN (front-end), then to map a DPN to an FPGA configuration (back-end). Finally, we present synthesis results on compute-intensive kernels from the Polybench suite. CCS Concepts: • Hardware → High-level and registertransfer level synthesis; • Theory of computation → Streaming models.
doi:10.1145/3446804.3446847 fatcat:pyhil53nuzg2hk2dc7pbj7zh6q