Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Bernd Becker, Rolf Drechsler, Stephan Eggersgluss, Matthias Sauer
2014 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)  
It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling a so-called SAT solver to compute a test. More recently, the potential of SAT-based ATPG has been significantly extended. In this paper, we first provide introductory knowledge on SAT-based ATPG and then report on latest developments enabling applications far beyond classical ATPG.
doi:10.1109/dtis.2014.6850674 dblp:conf/dtis/BeckerDES14 fatcat:xwlu3jwerjhjtdkq26cjdildpu