High performance computing on fault-prone nanotechnologies

Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this paper we introduce a new performance optimization dimension at the microarchitecture level which can mitigate overheads introduced by fault tolerance. This is achieved by directly exposing reliability versus delay design trade-offs while incorporating novel forms of speculation which use faster but less reliable
more » ... less reliable versions of a microarchitecture's performance critical components. Based on a parameterized microarchitecture, we exhibit the benefits of optimizing these tradeoffs.
doi:10.1145/1065579.1065649 dblp:conf/dac/ZykovMJVS05 fatcat:rwg3nt4oszh7xpxtzr6dq6vkta