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Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this paper we introduce a new performance optimization dimension at the microarchitecture level which can mitigate overheads introduced by fault tolerance. This is achieved by directly exposing reliability versus delay design trade-offs while incorporating novel forms of speculation which use faster but less reliabledoi:10.1145/1065579.1065649 dblp:conf/dac/ZykovMJVS05 fatcat:rwg3nt4oszh7xpxtzr6dq6vkta