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This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time constraints onto the heterogeneous multiprocessor System on Chip (SoC) architectures and focuses on a memory allocation step which is based on an integer linear programming model. An application is modeled as Kahn Process Network (KPN) whichdoaj:b8211922f0a64f35b745d94ebd811555 fatcat:klc3lpzgszcs5j253a7abmdrzy