Didactic architectures and simulator for network processor learning
Proceedings of the 2003 workshop on Computer architecture education Held in conjunction with the 30th International Symposium on Computer Architecture - WCAE '03
In our university, we are developing a project about Reconfigurable Network Processors (RNP). There are four important results: Reconfigurable CISC Network Processor (RCNP) architecture, Reconfigurable RISC Network Processor (R2NP) architecture, Network Processor Simulator (NPSIM), and a performance analytical model for the ISA (Instruction Set Architecture). The architectures and the simulator are not commercial products, but conceptual models. This paper shows the main functionality of those
... our results and the their applicability on the Network Processor learning. As our Network Processor architectures and simulator are simpler than commercial products, their conceptual models can aid students to learn network processors concepts, as a first step to understand other complex architectures. In this section we will describe the state-of-the-art of Network Processors. The main architecture features, the main functionalities, some related researches and companies. The main logic blocks (figure 1) of a Network Processor are: Multiple RISC processors, co-processors or programmable ASIC's; Dedicated hardware for network operations; High speed of memory interface; High speed of I/O interface; General-purpose processors interface. Each Network Processor has a typical architecture and uses some or all blocks showed. A Network Processor can use one RISC processor and coprocessors like the packet processors, or only multiple RISC processors. If the SoC technique is used, possibly dedicated hardwares like switching fabric and memory can be in the architecture. However, GPP interface like PCI and I/O interface always appear. It's an important detail, because a Network Processor needs to communicate to other processors (to help in system management) and the network (the main of functionality).