Flattened Butterfly Topology for On-Chip Networks

John Kim, James Balfour, William Dally
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip
more » ... . In addition, by exploiting the two dimensional planar VLSI layout, the on-chip flattened butterfly can exploit the bypass channels such that non-minimal routing can be used with minimal impact on latency and energy consumption. We evaluate the flattened butterfly and compare it to alternate on-chip topologies using synthetic traffic patterns and traces and show that the flattened butterfly can increase throughput by up to 50% compared to a concentrated mesh and reduce latency by 28% while reducing the power consumption by 38% compared to a mesh network.
doi:10.1109/micro.2007.29 dblp:conf/micro/KimBD07 fatcat:q7bbwgngnzcohoibbypf4ogb6u