A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is application/pdf
.
Flattened Butterfly Topology for On-Chip Networks
2007
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip
doi:10.1109/micro.2007.29
dblp:conf/micro/KimBD07
fatcat:q7bbwgngnzcohoibbypf4ogb6u