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Interval simulation: Raising the level of abstraction in architectural simulation
2010
HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture
Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This longstanding problem is further exacerbated in the multicore processor era. Existing solutions address the simulation problem by either sampling the simulated instruction stream or by mapping the simulation models on FPGAs; these approaches achieve substantial simulation speedups while simulating performance in a cycle-accurate manner. This paper proposes interval simulation which
doi:10.1109/hpca.2010.5416636
dblp:conf/hpca/GenbruggeEE10
fatcat:gjzjsmgz25ei7kd4sicd2v6vue