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Running parallel bytecode interpreters on heterogeneous hardware
2020
Conference Companion of the 4th International Conference on Art, Science, and Engineering of Programming
Since the early conception of managed runtime systems with tiered JIT compilation, several research attempts have been made to accelerate the bytecode execution. In this paper, we extend prior attempts by performing an initial analysis of whether heterogeneous hardware accelerators in the form of Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAS) can help towards achieving higher performance during the bytecode interpreter mode. To answer this question, we implemented a
doi:10.1145/3397537.3397563
dblp:conf/programming/FumeroSK20
fatcat:o3cu273o2rfhhf2iaivqqtpo2y