A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

S. Mathew, M. Anders, R.K. Krishnamurthy, S. Borkar
2003 IEEE Journal of Solid-State Circuits  
This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-T semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm
more » ... a good sub-130-nm scaling trend. Index Terms-Address generation unit (AGU), high-performance adders, semidynamic design, sparse-tree adder.
doi:10.1109/jssc.2003.810056 fatcat:35wvtrsexbc2lfbhjzzzxlsrju