A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

T.L. Brandon, J.C. Koob, L. van den Berg, Zhengang Chen, A. Alimohammad, R. Swamy, J. Klaus, S. Bates, V.C. Gaudet, B.F. Cockburn, D.G. Elliott
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder
more » ... tes 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.
doi:10.1109/tcsi.2009.2016592 fatcat:x7bzipwcijcr7b7vlgti5ywlte