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Hardware efficient architecture for compressed imaging
2014
IEICE Electronics Express
Compressed sensing has gained a wide application in image acquiring and reconstructing. Separable linear reconstruction has been shown to be effective in compressed imaging. This paper presents efficient hardware architecture based on adaptive sampling and separable reconstructing. By exploiting parallel properties in the architecture and timing scheme, high performance hardware has been proposed for both encoding and decoding sides. High performance Cholesky based matrix inversion has been
doi:10.1587/elex.11.20140562
fatcat:k6ek6655xnhonclatwck5uo63y