Implementation and Analysis of Optimized AES on FPGA

Nikita Purohit, Meghana A.
2017 International Journal of Computer Applications  
In today's world of digital transmission and reception of data and images high performance processing hardware is required. This paper presents an optimized AES algorithm for both software and hardware implementation through which the execution speed of the process is improved by reducing the cycle count. Optimized AES is implemented using softcore processor on FPGA Spartan-6 kit and the results are obtained using timing analyzer tool of Xilinx design suite 14.5. The execution time for hardware
more » ... implementation of optimized AES code is improved by 12.46% and 11.58% for encryption and decryption module respectively. Target device used for implementation of design is XILINX 14.5 platform studio xc6slx45-2csg324.
doi:10.5120/ijca2017914899 fatcat:4lqkrilt6veu7oayxynxownwp4