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Trace cache redundancy: red and blue traces
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)
The objective of this paper is to improve the use of the hardware resources of the trace cache mechanism, reducing the implementation cost with no performance degradation. We achieve that by eliminating the replication of traces between the instruction cache and the trace cache. As we show, the trace cache mechanism is generating a high degree of redundancy between the traces stored in the trace cache and those built by the compiler, already present in the instruction cache. Furthermore, code
doi:10.1109/hpca.2000.824361
dblp:conf/hpca/RamirezLV00
fatcat:3rsuy6qfhjh4jnj4sjtqdlbscy