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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kss7mrolvja63k4rmix3iynkzi" style="color: black;">IFIP Advances in Information and Communication Technology</a>
Advancing technology impacts design along several vectors. Interconnect delay became dominant in many designs at O.18J.1I1l; to obtain timing closure, it was necessary to unify synthesis and placement. Moving forward, increasing degradation of signal integrity will be caused by capacitive cross coupling, by inductive effects and by several other physical effects. This will require the integration of fast and accurate analysis that can drive avoidance and correction of signal integrity problems<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-0-387-35597-9_8">doi:10.1007/978-0-387-35597-9_8</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/re5jice2l5cxtmcgyggg3aglyi">fatcat:re5jice2l5cxtmcgyggg3aglyi</a> </span>
more »... rimarily in routing, as well as in synthesis and placement. Advancing technology also means increasing complexity. Verification is particularly affected by technology as exemplified by the ever-increasing simulation needs. Using hundreds of millions of devices effectively will be possible only by reusing pre-designed intellectual property (lP) effectively and by addressing system-level issues in EDA. This presentation poses EDA solutions to these challenges, gives concrete examples, and argues that complete solutions, rather than point tools, will increasingly and justifiably dominate the EDA field. © IFIP International Federation for Information Processing 2002 M. Robert et al. (eds.), SOC Design Methodologies
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