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Optimizing routability in large-scale mixed-size placement
2013
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
One of the necessary requirements for the placement process is that it should be capable of generating routable solutions. This paper describes a simple but effective method leading to the reduction of the routing congestion and the final routed wirelength for large-scale mixed-size designs. In order to reduce routing congestion and improve routability, we propose blocking narrow regions on the chip. We also propose dummy-cell insertion inside regions characterized by reduced fixed-macro
doi:10.1109/aspdac.2013.6509636
dblp:conf/aspdac/CongLTX13
fatcat:jq3wvpb3zzh5ldbp2zbjojjryi