A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
Consolidating Security Notions in Hardware Masking
2019
Transactions on Cryptographic Hardware and Embedded Systems
In this paper, we revisit the security conditions of masked hardware implementations. We describe a new, succinct, information-theoretic condition called d-glitch immunity which is both necessary and sufficient for security in the presence of glitches. We show that this single condition includes, but is not limited to, previous security notions such as those used in higher-order threshold implementations and in abstractions using ideal gates. As opposed to these previously known necessary
doi:10.13154/tches.v2019.i3.119-147
dblp:journals/tches/MeyerBR19
fatcat:cn3vamlocrfjldkowuagmiwi2q