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Efficient pipelining for modular multiplication architectures in prime fields
2007
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2
doi:10.1145/1228784.1228911
dblp:conf/glvlsi/MentensSPV07
fatcat:4yhww4hi3vhkxi4nfkybbd4iae