In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-2/3 prescaler is investigated. Based on this analysis, a new ultra low power wide band 2/3 prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed 2/3 prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit

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... er of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-2/3 unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively. Index Terms-DFF, frequency synthesizer, E-TSPC, true single-phase clock(TSPC), high speed digital circuits, Dual modulus prescalers.