A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

A. Cevrero, C. Aprile, P. A. Francese, U. Bapst, C. Menolfi, M. Braendli, M. Kossel, T. Morf, L. Kull, H. Yueksel, I. Oezkaya, Y. Leblebici (+2 others)
2015 2015 Symposium on VLSI Circuits (VLSI Circuits)  
This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7x8-tap cross decisionfeedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The
more » ... t TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER < 10 −12 with 12.5%UI margin. It occupies 300x350µm 2 with an energy efficiency of 5.9mW/Gb/s.
doi:10.1109/vlsic.2015.7231267 dblp:conf/vlsic/CevreroAFBMBKMK15 fatcat:kdqjy2jjznbqfowtoxzjbx2uga