An Effective Overlap Removable Objective for Analytical Placement
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
A High-Precision Quadrature Modulator and High-Performance RF Front-End Circuits suitable for Multi-band Wireless Transceivers: Recently the demand for wireless systems such as sensor networks has been rapidly growing. However, radio-wave resources are limited and invaluable especially in these days. Therefore, software-defied radios (SDRs) and cognitive radios, which is a principal application of SDR, can be the key to greatly improving frequency-spectrum efficiency. SDRs demand flexibility
... reconfigurability in RF (Radio Frequency) circuits. Therefore, a spectrum-efficient wireless transceiver architecture is indispensable. In this research, we proposed a multi-band wireless transceiver using a high-precision complex quadrature modulator (HP-CQMOD) and a flexible-filtering receiver suitable for sensor networks. As the final goal of our research, we would like to establish a reconfigurable wireless communicator, whose frequency band can be changed according to communication conditions and/or a country s regulations using reconfigurable RF and baseband processors and downloadable software. This is a kind of cognitive radios based on SDR (Software-Defined Radios). In recent years, multi-level modulations such as Quadrature Amplitude Modulation (QAM) are or will be used in Wireless LANs, digital TVs, and the 4th-generation cell-phones. So, very small modulation errors of QMOD are strongly demanded. In the 2013, we concen-78 Division of Computer Engineering trated on circuit design of low-power HP-CQMODs and linear power amplifiers in the transmitter, and have started research on frequencyshift filtering methods. Moreover, we devised low-distortion receiver front-end circuits and designed digitally-controlled oscillators (DCOs) and time-to-digital converters (TDCs) for all-digital PLLs (ADPLL) for carrier-signal generation. RF/IF building blocks we designed have three features as follows: 1. Low-power high-precision complex quadrature modulators are newly developed, featuring folded-cascode frequency divider used for a 90dgree phase shifter and passive quadrature mixers. 2. We proposed linear CMOS power amplifiers using compensation techniques for transconductance and capacitance non-linearities. 3. Low-distortion and wideband techniques were devised for RF lownoise amplifiers and mixers. Yukihide Kohira: We investigate design automation methodology for LSI circuits. Due to the increase of scales of LSI circuits and the decrease of time to market of LSI products, design automation systems are widely used in order to design LSI circuits. Since the performance of LSI depends on the used design automation systems, it is important to develop design automation methodology continuously in order to obtain good products. Our research interests are design automation for clock synchronous framework and layout design. In 2013, we focused on following four topics. General-synchronous Framework In general-synchronous framework, a clock is distributed periodically to all registers but the clock is not necessarily distributed simultaneously. General-synchronous framework is expected to obtain LSI circuits with high performance and low power consumption. The target of this research is to establish a design automation system for generalsynchronous framework. In 2013, we investigated clock scheduling in which the number of clock domains is restricted to two to obtain circuits with high performance without increasing power consumption and an implementation method of circuits into FPGA in general-synchronous framework. In our experiments, circuits with higher performance were obtained by the proposed methods. 79 Division of Computer Engineering Deskew In resent LSI circuits, process variations increase significantly because of the progress of the process technology. The process variations significantly cause delay variations and delay variations affect the performance and the yield of VLSI chips. If the circuit cannot work at the testing process after the fabrication of LSI chips, the circuit can be recovered by deskew in which delay of the programmable delay elements is adjusted. The target of this research is to establish a design automation system for deskew which can improve the yield of LSI chips. In 2013, we proposed the delay turning method in which the programmable delay elements with an ordered finite set of delay values and confirmed that the proposed method improved the yield. Placement In the recent LSI design, it is difficult to obtain a placement which satisfies both design constraints and specifications due to the increase of the circuit size, the progress of the manufacturing technology, and the speed-up of the circuit performance. Analytical placement methods are promising to obtain the placement which satisfies both design constraints and specifications. The target of this research is to establish a placement methodology to satisfy both design constraints and specifications in short computational time. In 2013, we proposed an acceleration method by GPGPU for an analytical placement method and confirmed that the proposed method was about ten times faster than the conventional sequential programming. Lithography Litho-Etch-Litho-Etch (LELE) type double patterning which seems to be most practical solution for the 22 nm node enables us to fabricate smaller features without using advanced technologies such as extreme ultraviolet (EUV) lithography. In LELE type double patterning, a layout pattern is decomposed and assigned to two masks so that each can be formed on a wafer by an exposure. The yield which affects manufacturing cost much depends on a layout pattern decomposition. A layout pattern decomposition method needs to have an ability to achieve higher yield. The target of this research is to establish a design automation system for advanced lithography such as LELE type double patterning to improve the yield. In 2013, we proposed a fast layout decomposition algorithm in LELE type double patterning considering the yield. Our proposed algorithm obtained a layout decomposition with mini- 80 Division of Computer Engineering mum cost efficiently for higher yield. In our experiments, our proposed algorithm was 7.7 times faster than an existing method on average. In the recent LSI design, it is difficult to obtain a placement which satisfies both design constraints and specifications due to the increase of the circuit size, the progress of the manufacturing technology, and the speed-up of the circuit performance. Analytical placement methods are promising to obtain the placement which satisfies both design constraints and specifications. Although existing analytical placement methods obtain the placement with the short wire length, the obtained placement has overlap. In this paper, we propose Overlap Removable Area as an overlap evaluation method for an analytical placement method. Experiments show that the proposed evaluation method is effective for removing overlap in the analytical placement method.