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A methodology and analytic expressions are proposed to appropriately allocate the available physical area to through silicon vias (TSVs) and sleep transistors in three-dimensional (3D) ICs with power gating. Power supply noise is minimized by the proposed resource allocation methodology while satisfying the required constraints on leakage current and turn-on time. A comprehensive simulation setup of a three plane 3D IC is developed to evaluate the accuracy and efficacy of the proposeddoi:10.1109/isqed.2015.7085481 dblp:conf/isqed/WangS15a fatcat:visubg75hfhhjdumda2mhjpogi