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This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributeddoi:10.1109/iscas.2012.6271624 dblp:conf/iscas/YangLHLCCCHJLLLSWLH12 fatcat:gnaqy6w37bdctng6qjlm3bx22a