High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee (+4 others)
2012 2012 IEEE International Symposium on Circuits and Systems  
This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed
more » ... timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.
doi:10.1109/iscas.2012.6271624 dblp:conf/iscas/YangLHLCCCHJLLLSWLH12 fatcat:gnaqy6w37bdctng6qjlm3bx22a