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Verification of floating-point adders
[chapter]
1998
Lecture Notes in Computer Science
The floating-point(FP) division bug in Intel's Pentium processor and the overflow flag erratum of the FIST instruction in Intel's Pentium Pro and Pentium II processor have demonstrated the importance and the difficulty of verifying FP arithmetic circuits. In this paper, we present the verification of FP adders with reusable specifications, using extended word-level SMV, which is improved by using the Multiplicative Power HDDs (*PHDDs), and by incorporating conditional symbolic simulation as
doi:10.1007/bfb0028769
fatcat:fzuqaefv4jgkvl25gkix36muwi