A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing

Chung-chi Lin, Ming-hwa Sheu, Huann-keng Chiang, Zeng-chuan Wu, Jia-yi Tu, Chia-hung Chen
2008 2008 International Conference on Embedded Software and Systems  
This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves
more » ... 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 25980 gates in a 450 × 450μm 2 chip is able to process digital image scaling for HDTV in real-time.
doi:10.1109/icess.2008.85 dblp:conf/icess/LinSCWTC08 fatcat:wwgzb2odgrfujclnm4ogkt4oxq