Power Supply Noise in SoCs: Metrics, Management, and Measurement

Karim Arabi, Resve Saleh, Xiongfei Meng
2007 IEEE Design & Test of Computers  
&THE IC INDUSTRY is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. Unfortunately, these advanced technologies pose new and sometimes unexpected challenges to the semiconductor industry. Current DSM problems of excessive power dissipation, voltage-drop effects, coupling noise, and decreasing production yield will continue and will likely get worse. This has led to the development of SoC design methodologies to deal
more » ... the problems of complexity and productivity. 1 As a result, the SoC design bottleneck in DSM technologies is shifting away from reusable IP design and integration to physical design and verification of the overall system. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. However, increasing operating frequencies and power densities in 90-nm and 65-nm ICs lead to a higher percentage of voltage drops in the power grid. Simultaneous switching of I/O blocks and core logic causes large, rapid changes in supply current. The level and change rate of current are the two main sources of power supply noise. At the same time, circuit tolerance to voltage drop in DSM technologies is decreasing as a result of lower logic noise margins. This is because threshold voltages do not scale down as fast as supply voltages as the technology geometry scales down. A constantly varying V DD or V SS voltage profile introduces unpredictability in the timing behavior of logic gates, making design sign-off difficult. Furthermore, large, instantaneous voltage drops on power supply rails can render standard cells and memory circuits inoperable and lead to unexpected behavior. Power consumption and power supply noise will likely be the two main challenges of semiconductor design over the next few years. Here, we are concerned with maintaining the power integrity of DSM designs. Voltage drop in the power grid is due to two components: IR and Ldi/dt. R represents the resistances of the power mesh network, power pads, and device package. L represents the inductances of the power mesh network, power pads, and device package. Our goal is to provide useful information to properly manage supply noise in large SoCs. In the past, analysis techniques and design metrics dealing with power supply voltage drop were simplistic. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations, leading to either unnecessary overdesign or risk of timing failures. Dynamic voltage drop (DVD) analysis is emerging as a replacement of SVD analysis for capturing the impact of power supply noise on the timing behavior of logic and memory cells. However, neither approach has been fully justified or validated. To better understand the impact of power supply noise on performance, it is critical to monitor and measure power supply noise on silicon. The next step is to reduce overall power supply noise, which can be accomplished in many ways. Among physical design 236 Editor's note: Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of predictability is complicating timing closure, physical design, production test, and speed grading of SoCs. This article describes and validates two metrics that quantify the impact of power supply noise. -Mohammad Tehranipoor, University of Connecticut IR-Drop and Power Supply Noise Effects in Very Deep-Submicron Designs 0740-7475/07/$25.00 G 2007 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers and circuit techniques for reducing power supply voltage drop are improving power supply mesh design, increasing the number of power supply pins, inserting decoupling capacitors (decaps), and integrating voltage regulators. Introducing useful skew to stagger high-activity clocks and buffers across the chip and restructuring the design to reduce rapid changes in the switching profile are also methods designers use to deal with power supply noise. In this article, we present our research results on power supply noise metrics, management, and measurement. We also present experimental results we gathered from chips in production. Power supply noise analysis metrics SVD analysis and verification have been an essential part of the physical design and verification flow in the semiconductor industry for more than 10 years. In this approach, the circuit's transistors or blocks draw their average current from the power grid, and the IR drops across the chip are computed using these average currents. The computed fixed values are fed to timing verifiers, which assess the impact of the IR drops on delay. SVD analysis has provided useful feedback in terms of certain glaring errors in the power grid design. However, at 90-nm and smaller technologies, SVD verification is not enough to ensure power integrity. It doesn't take into account the contribution of power density, variations in switching-activity profile, and impact of inductance and decaps, including LC resonance effects. 2 Therefore, it is inadequate for analyzing and optimizing power delivery networks in SoC designs. Recently, industry began to use DVD analysis to capture the impact of decaps, inductance, and spatial and temporal switching events in the design. DVD analysis does not return a fixed value and therefore cannot be easily assessed or back-annotated into timing-analysis engines. Currently, there is no sign-off or analysis metric to characterize a DVD profile. This lack of suitable metrics for DVD makes it difficult to compare different DVD profiles and take appropriate design action, in terms of engineering change orders, to improve the DVD profile. We propose and validate the use of two metrics to qualify a DVD profile and its impact on a design's timing performance. The DVD avg metric is the DVD profile's average value in the timing cycle, and DVD max is the DVD profile's peak value in the timing cycle. These simplified metrics are design optimization indications that accelerate the design process. Users should add design margins to these metrics to account for their simplifications, or they should perform the final sign-off process with actual DVD profiles. Although these two metrics seem obvious, there has been little analysis to support their use. Here, we show that DVD avg correlates with the design's timing slowdown and should be set to the design's timing margin (as a percentage of the clock cycle). The DVD max value represents the minimum voltage drop that causes a functional failure in the behavior of memory cells or standard cells. That is, if the voltage drop exceeds DVD max , the behavior of standard cells or memory cells will be unpredictable. Therefore, the value of DVD max depends on the tolerance of individual standard cells or memory cells to voltage drop. In our design environment, we have determined that DVD avg should not exceed 5% of V DD -V SS , and DVD max should not exceed 20% of V DD -V SS . These limits are pessimistic enough to account for the simplified nature of these metrics. The voltage drop profiles of different instances of critical paths are almost similar to one another, given the behavior of timing-driven placement engines that tend to cluster instances of the same path in close proximity to facilitate timing closure. Therefore, we can safely assume that all instances of a critical path see the same DVD profile. In corner cases, where this assumption is not true, designers must analyze DVD avg and DVD max for all instances of critical paths in the timing window of each instance. The timing window for each instance is where the instance is actually switching. To support these two metrics, we first establish that the effect of the voltage drop profile on a digital path's timing performance is equivalent to applying a fixed supply voltage of V DD -DVD avg to the same path. In other words, we first simulate a logic path in the presence of the true dynamic voltage profile on the power supply. Then, we use a DC voltage equal to the average of the voltage profile on the power supply and show that the timing behavior of the two cases will match. Figure 1 illustrates the intuitive reason for this relationship. Consider the delay of the critical path of the circuit between the two flip-flops. Clearly, gate delay decreases when supply voltage overshoots, and increases when supply voltage undershoots. When supply voltage fluctuates, gates that see a voltage drop higher than V DD -DVD avg will accelerate, and gates that see a voltage drop lower than V DD -DVD avg will decelerate, compared with the situation in which all gates see a voltage drop equal to V DD -DVD avg . Because paths consist of several gates, we assume that the law of averages applies: Delay variations in the path are equalized to the average of the delay variations of each gate in the path. For this assumption to hold, the relationship between gate delays and voltage around the nominal point should be linear, and the path considered should span the entire clock cycle, averaging the entire voltage profile, not just a portion. We find that the assumptions of linearity and path-averaging effects are valid because power supply noise is analyzed up to DVD max 5 20% (keeping gate delays almost linearly proportional to V DD ), and we are interested in critical paths by default. We validated these assumptions on several industrial designs by simulating the extracted layout of their paths in Spice with detailed voltage drop profiles and with V DD -DVD avg . We used a commercial DVD analysis tool to obtain detailed supply voltage profiles of the paths. We selected three critical paths in different physical locations of a communication chip that uses a 90-nm CMOS process with a 1.0-V supply and simulated various data activities to create DVD profiles with different shapes. We simulated the extracted critical paths with the true profile and its equivalent V DD -DVD avg . Figure 2 shows the results for one path. For each profile tagged V DD -DVD avg , we simulated the path with the actual DVD profile and its equivalent DC voltage of V DD -DVD avg . The figure uses points to represent the simulation results for the true profile simulation, and a solid line to represent simulation results with the DC voltage of V DD -DVD avg . The difference between timing performances is less than 1% for all simulated cases. In all our critical paths, the DVD profiles for different instances of the critical path have similar characteristics. We also simulated each instance with its own DVD profile and observed no noticeable change in results. The results reveal a strong linear relationship over the range shown and indicate roughly that a 5% to 10% change in V DD leads to a 5% to 10% change in delay. By analyzing different DVD profiles using these metrics, we reached an important conclusion: The Ldi/dt contribution of voltage drop is not as critical as the IR contribution. Ldi/dt affects only DVD max and thus has minimal impact on DVD avg as long as the charge transfer is completed within the cycle. Therefore, Ldi/dt voltage drop doesn't play a major role in the chip's timing performance as long as it doesn't create supply fluctuations that exceed DVD max . The two metrics let us compare and qualify DVD profiles and optimize designs more effectively to improve timing margins. The behavior described by DVD avg is fundamental and originates from the nature of cells responding to voltage variations. This behavior of cells responding to the average power supply voltage should hold at least for 65-nm technology. Armed with this knowledge, the designer's next step is to reduce supply noise. Reducing power supply noise Here, we focus on decaps and the new design considerations necessary as technology scales below 90 nm. Among power supply noise reduction techniques, inserting decaps is the most common. Decaps hold a reservoir of charge and are placed around regions of high current demand. When large drivers switch, nearby decaps provide a source of current that reduces IR and Ldi/dt voltage drops to keep the target average and peak supply voltages within their noise budgets (DVD avg and DVD max ). White-space decaps, 238 Figure 1. Dynamic voltage drop profile across a cycle. Figure 2. Dynamic voltage profile simulation (solid line) versus V DD -DVD avg (points) for a critical path in a communication chip design. IR-Drop and Power Supply Noise Effects in Very Deep-Submicron Designs IEEE Design & Test of Computers which usually consist of NMOS transistors, are placed between blocks in the open areas of the chip. In contrast, standard-cell decaps use both NMOS and PMOS devices and are placed within the logic blocks themselves. Figure 3 shows a decap formed by an NMOS transistor. This decap is modeled as a lumped RC circuit, in which C determines the charge available and R determines the transient response of charge delivery to the switching circuit. 3 Effective capacitance C eff and effective channel resistance R eff at low frequencies are Here, C ox is the oxide capacitance per unit area, C ol is the sum of overlap and fringing capacitances per unit width, m is the channel mobility, V TH is the threshold voltage, and W and L are the transistor's width and length. 4 Both R eff and C eff are functions of the operating frequency, f. This was not an important issue in earlier technologies, but, as f increases, it is important to recognize that these values will not be constant. For example, consider a fixed-area decap with changing W and L. While the transistor area is fixed, the lowfrequency capacitances and resistances will change from one layout to another according to Equations 1 and 2. We used Spice to plot the frequency characteristics of NMOS and PMOS decaps. Typical high-speed clock rates today are in the GHz range, but it is important to study frequency response well beyond clock frequency. Most of the spectral power density of digital signals lies within frequencies of up to f knee 5 1/(2t rise ), where t rise is a signal's rise time (on the order of 50 ps or less), and f knee is the 3-dB cutoff frequency of the spectral power density. 5 We assume conservatively that t rise 5 50 ps, and we carry out the analysis up to 10 GHz. As Figure 4 shows, both R eff and C eff decay in value as frequency increases. The reason for this is that the charge in the MOSFET channel cannot change instantaneously, because mobile carriers from the source and the drain take a finite amount of time to form the inversion layer. The channel charge's response time is controlled by the device's transit time, which is quadratically related to channel length. At high frequencies, the channel charge cannot respond fast enough to match the gate charge, causing an effective degradation in capacitance value. Both NMOS and PMOS devices with long channels have similar characteristics, but the effect is far more pronounced in PMOS devices. For example, when L 5 32l, the capacitance drops off noticeably because the device cannot provide the charge in the channel at the rate demanded by voltage changes at the gate. At 10 GHz, the NMOS device's capacitance drops by 20%, whereas the PMOS device's capacitance drops by 80%. This implies that decaps should be designed with smaller L values, requiring the use of multiple parallel devices, commonly known as fingered layouts. For example, one device with L 5 32l can be laid out with four devices, each with L 5 8l. PMOS devices must use roughly twice as many fingers to achieve the same performance as NMOS. You can understand this intuitively by comparing the responses of L 5 32l for NMOS with L 5 16l for PMOS. Unfortunately, the use of fingers increases the number of contacts and increases the area. The area penalty can be severe, so a suitable L must be selected-one that trades off area and frequency response. At the 90-nm technology node, two new problems arise because oxide thickness t ox decreases to 2.0 nm or less. A large voltage drop across the thin oxide introduces gate-tunneling leakage 6 and potential electrostatic discharge (ESD) breakdown. 7 Higher gate-tunneling leakage through decaps increases the chip's total static-power consumption. An ESD event across the thin gate oxide increases the likelihood of permanent damage to the IC. We can determine gate leakage levels with BSIM4 Spice models. Using a 90-nm technology with a 2.0-nm oxide thickness and a 1.0 V power supply, we can estimate the corresponding gate leakage current density, J, as 3 3 10 27 A/mm 2 for NMOS and 239 Figure 3. Decoupling capacitor (decap) modeled as a lumped RC circuit. 1 3 10 27 A/mm 2 for PMOS. Thus, PMOS gate leakage is roughly three times smaller than NMOS gate leakage for the same-size transistors. Gate leakage contributes to total static-power consumption, and decaps usually occupy a large onchip area. White-space decaps (those located outside the standard-cell blocks) can be implemented using a thicker oxide, greatly reducing leakage and ESD, but typically consume three times more area. Standard cells require the use of thin-oxide decaps because the decaps are embedded in the logic blocks. A possible solution is to use only PMOS devices for standard-cell decaps, because they leak less. However, this is not a viable solution for high-performance circuits, because PMOS devices have a poorer frequency response than NMOS devices. Standard-cell decaps at 90 nm also require modifications for ESD protection. ESD is a transient process of static-charge transfer that can arise from human contact with an IC pin. Typically, about 0.6 mC of charge is carried on a body capacitance of 100 pF, generating a potential of 2 kV (or higher) to discharge from the contacted IC pin to ground for a duration of more than 100 ns. 7 When running simulations of an ESD event, the designer can measure oxide voltage and compare it with a device's oxide breakdown voltage for a given technology. Oxide breakdown voltage is almost linearly proportional to oxide thickness. 7 For instance, a 90-nm process using t ox 5 2.0 nm has an oxide breakdown voltage of around 5 V. If thickness doubles, oxide breakdown voltage also doubles to around 10 V. In an ESD protection scheme for decaps, a series resistance R in is required as a protection element. This resistance limits the maximum voltage possible at its gate, where ESD damage would occur. Of course, inserting a large R in dramatically reduces its frequency response and transient response. Consequently, designers must consider the trade-off between ESD protection and decap response time. To address the issue of ESD reliability, cell library developers have proposed a cross-coupled decap. This design provides better ESD protection by having a larger effective resistance without additional area. 240 Figure 4 . Effective capacitance C eff and effective resistance R eff of decaps in 180 nm: NMOS C eff (a), PMOS C eff (b), NMOS R eff (c), and PMOS R eff (d).
doi:10.1109/mdt.2007.79 fatcat:prvja65hhrfwbiecdr3ol32w6a