One of the most sev ere shortcomings of currently av ailable equiv alence checkers is their inability to v erify arithmetic circuits and multipliers, in particular. In this paper, we present a bit-lev el rev erse-engineering technique that complements standard equiv alence checking frameworks. W e propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit-lev el representation of the circuit is obtained, equiv

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... alence checking can be performed using simple arithmetic operations. W e hav e successfully applied the technique for the v erification of a large number of multipliers of different architectures as well as more general arithmetic circuits, such as multiply/add units. The experimental results show the great promise of our approach. Index T erms-Arithmetic bit lev el, arithmetic circuit, datapath v erification, equiv alence checking, formal hardware v erification, multiplier.