Minimizing inductive noise in system-on-a-chip with multiple power gating structures

Suhwan Kim, S.V. Kosonocky, D.R. Knebel, K. Stawiasz, D. Heidel, M. Immediato
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)  
A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off of its sleep transistor.
more » ... perimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique.
doi:10.1109/esscirc.2003.1257215 fatcat:fphfj6g6cvaztameqi7fqcs55m