On-chip interconnections: impact of adjacent lines on timing

Deschacht, G. Servel
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)  
As the CMOS technology scales down, the coupling capacitance between adjacent wires plays dominant part in wire load and interference becomes a serious problem for VLSI design. In this pape r, we focus on delay increase caused by adjacent lines. This increase in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. We propose an analytical expression to compute the delay in the presence of coupling that takes explicitly into account interconnect
more » ... nt interconnect resistance and capacitance, driver resistance and relative driver strengths.
doi:10.1109/aspdac.2001.913364 fatcat:wyhubmcpzfapvltnuf5n6t5vme