We present a boolean technique to reduce p ower consumption of combinational circuits that have already been optimized for area and delay and then mapped onto a library of gates. In order to achieve a better optimization, we cluster gates by collapsing two or more levels of gates into a single node. When optimizing each cluster, our method extends the algorithms used i n espresso, b y adding heuristics that bias the minimization toward lowering the power dissipation in the circuit. The results

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... f our method, on a number of benchmark circuits, show an average of 16% improvement in power savings compared to existing boolean techniques.