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Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide

Jongwoo Kim, Hyungjun Jo, Yonggyu Cho, Hyunyoung Shim, Jaesung Sim, Hyungcheol Shin
2022 IEICE Electronics Express  

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In 3-D charge trap (CT) NAND flash memory, program/erase (P/E) cycling tests are performed, and the degradation of cell characteristics is investigated. The mechanism of mid-gap voltage (Vmg) shift difference between erased state and programmed state is presented and it is verified by technology computer-aided design (TCAD) simulation configured identically to the real device. TCAD simulation also makes it possible to extract the trap density through the current fitting. Generation of interface
more » ... traps (Nit) and bulk traps in the tunneling oxide (Not) has the form of a power-law of the number of P/E cycles. Furthermore, it is experimentally found that the degradation of cell characteristics is mainly caused by hole tunneling current from the poly-silicon channel during erase operation.
doi:10.1587/elex.19.20220465 fatcat:oclcskriyzdrbadqzkw7xfnibq
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Jongwoo Kim, Hyungjun Jo, Yonggyu Cho, Hyunyoung Shim, Jaesung Sim, Hyungcheol Shin. "Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide." IEICE Electronics Express (2022)