A pipelined memory architecture for high throughput network processors

T. Sherwood, G. Varghese, B. Calder
30th Annual International Symposium on Computer Architecture, 2003. Proceedings.  
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom ASICs. We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network
more » ... rithms. Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.
doi:10.1109/isca.2003.1207008 dblp:conf/isca/SherwoodVC03 fatcat:7lwqkhax35e5zhgferbkfnehg4