A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency

Xiaoyao Liang, David Brooks, Gu-Yeon Wei
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
Process variation will greatly impact the power and performance of future microprocessors. Design approaches based on multiple supply or threshold voltage assignment provide techniques to statically tune critical path delays for energy savings [1]. However, under process variation, the delay of critical paths may vary, and a large number of critical paths in circuits reduces the maximum operating frequency of pipelined processors. One proposed postfabrication solution is to adaptively tune the
more » ... ack-body bias to combat variations for logic structures [2] . Dynamic voltage switching between two power supplies, using level shifters to cross voltage domains, has also been proposed to primarily reduce power [3] [4] [5] . This paper explores two fine-grained, post-fabrication circuittuning techniques to combat process variation for pipelined logic components-voltage interpolation and variable latency. These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13µm CMOS logic process with 8 metal layers. Measured results from fabricated chips show that both techniques provide wide frequency tuning range to deal with frequency fluctuations arising from process variations with minimal power overhead, and in some configurations, power savings.
doi:10.1109/isscc.2008.4523228 dblp:conf/isscc/LiangBW08 fatcat:arzyakh7srbg5hrxq2uf2npmjq