Comparison of Reduced-Order Interconnect Macromodels for Time-Domain Simulation

T. Palenius, J. Roos
2004 IEEE transactions on microwave theory and techniques  
A typical integrated-circuit model consists of nonlinear transistor models and large linear RLC networks describing the interconnects. During the last decade, various model-reduction algorithms have been developed for replacing each RLC network with an approximately equivalent, but much smaller, model. Since these reduced-order models are described in the frequency domain, they have to be linked to the transient analysis of the whole nonlinear circuit, which can be done by replacing these
more » ... with appropriate macromodels. In the interconnect literature, the actual macromodel realization, which has a great impact on the transient-simulation CPU time, is often overlooked. This paper presents a comprehensive comparison of nine reduced-order interconnect macromodels for time-domain simulation: the macromodels are reviewed, presented in a unified manner, and compared both theoretically and numerically. Since we have implemented all the nine macromodels into the APLAC circuit simulation and design tool, we are able to present a fair and meaningful CPU-time comparison.
doi:10.1109/tmtt.2004.834562 fatcat:h4nvxtnfbjgc5am3jsutvi64z4