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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/zwrt4lmoffgrpejt4mmp2p34kq" style="color: black;">2009 International Conference on High Performance Computing (HiPC)</a>
Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typically split into multiple banks and these banks are either connected through a bus (uniform cache access -UCA) or an onchip network (non-uniform cache access -NUCA). Irrespective of the cache model (NUCA or UCA), the complex interconnects that must be navigated within large caches are found to be the dominant part of<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/hipc.2009.5433222">doi:10.1109/hipc.2009.5433222</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/hipc/UdipiMB09.html">dblp:conf/hipc/UdipiMB09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/e4qmsg74wjcbzctvrr6dbgqzly">fatcat:e4qmsg74wjcbzctvrr6dbgqzly</a> </span>
more »... e access power. While there have been a number of proposals to minimize energy consumption in the inter-bank network, very little attention has been paid to the optimization of intra-bank network power that contributes more than 50% of the total cache dynamic power in large cache banks. In this work we study various mechanisms that introduce low-swing wires inside cache banks as energy saving measures. We propose a novel non-uniform power access design, which when coupled with simple architectural mechanisms, provides the best power-performance tradeoff. The proposed mechanisms reduce cache bank energy by 42% while incurring a minor 1% drop in performance.
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