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A Novel Post-Silicon Debug Mechanism Based on Suspect Window
2010
IEICE transactions on information and systems
Bugs are becoming unavoidable in complex integrated circuit design. It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges. Scan-based debug mechanism provides high observability by reusing scan chains. However, it is not feasible to scan dump cycle-by-cycle during program execution due to the excessive time required. In fact, it is not necessary to scan out the error-free states. In this
doi:10.1587/transinf.e93.d.1175
fatcat:d3ygiydqgrgrlbeu5l3hpormea