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Lecture Notes in Computer Science
Statistical Static Timing Analysis (SSTA) is becoming necessary; but has not been widely adopted. One of those arguments against the use is that results of SSTA are difficult to make use of for circuit design. In this paper, by introducing conditional moments, we propose a path-based statistical timing approach, which permits us to consider gate topology and switching process induced correlations. With the help of this gate-to-gate delay correlation, differences between results of SSTA anddoi:10.1007/978-3-642-11802-9_6 fatcat:dd5ey5hcofebpbspiryns6p4jy