A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture

Niklas U. Andersson, Mark Vesterbacka
2014 IEEE Transactions on Circuits and Systems - II - Express Briefs  
A new Vernier time-to-digital converter architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells allowing the architecture to be implemented in FPGAs, digital synthesized ASICs, or in full custom design flows. To
more » ... sign flows. To demonstrate the proposed concept, a 7-bit Vernier time-todigital converter has been implemented in a standard 65 nm CMOS process with an active core size of 33 µ µ µm × 120 µ µ µm. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.
doi:10.1109/tcsii.2014.2345289 fatcat:ybzzxrzco5horhs5co7msf5ioa