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Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needsdoi:10.1145/339647.363382 fatcat:ymase3zpnfhjbclxdatm3voq7m