From RTL to silicon: The case for automated debug

Andreas Veneris, Brian Keng, Sean Safarpour
2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)  
Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap.
more » ... ary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task.
doi:10.1109/aspdac.2011.5722204 dblp:conf/aspdac/VenerisKS11 fatcat:hhjgjbu6ijdlrmq3325y64uogi